DESIGN IMPROVED PERFORMANCE OF WALLACE TREE MULTIPLIER AND ITS APPLICATIONS: A STUDY

Abstract

In this paper we examine the design improved performance of Wallace Tree Multiplier and its applications. Multipliers are complicated units that determine the total field, speed, and power consumption of digital designs of electronics. This paper compares numerous existing Wallace tree multiplier designs with the proposed Wallace Tree Multiplier in terms of latency, complexity, and power consumption. It was found that the proposed Wallace tree configuration reduces power dissipation by approximately 70%, the power delay product by approximately 88.7%, and the amount of transistors by approximately 60.9 percent. With the advent of digital machines, multipliers have become increasingly important in various fields of engineering and medical sophisticated equipment. Multipliers are often used in optical signal processing and microprocessor architectures. Multipliers, in comparison to addition and subtraction, need more time and hardware energy.