A Novel Approach to Generate Combinational ATPG using Genetic Algorithm

Abstract

 Testing is an important part of any digital IC design process. It is important to determine the faults and to diagnose the fault in an IC. A test vector is a set of inputs provided to the IC in order to test it. Generally test vector generation is a program used to automatically generate test data for use in automated testing circuits. This can generate many individual test vectors. Manual testing can be done for smaller designs, in which inputs can be given to the system by forcing the values and observing the output. As the complexity of the design increases the testing becomes tedious and hence automation is required. In VLSI testing we need Automated Test Pattern Generator (ATPG) to get input test vectors for the Device Under Test (DUT). In this paper we present a new way generate ATPG vectors using probability weights and find the optimal set of vector for the weights using genetic algorithm(GA) on excess three encoder as our DUT. The excess three encoder was simulated for stuck at fault modelling. We find that our approach has yielded promising results compared to other ATPG algorithms.